1. Field of the Invention
The present invention relates to semiconductors and more particularly to a method for fabricating integrated circuits with self-aligned contacts.
2. Description of the Prior Art
Large-scale MOS integrated circuits, often having thousands of MOSFETs on a single semiconductor chip, must have a plurality of electrically conductive contacts, through insulation overlying the surface of the semiconductor material, to the active and passive regions in this material to provide the necessary interconnection between circuit lines, source-drain regions and gate electrodes of individual transistor elements. Using prior art techniques, it is necessary to make oversized conductive areas in the semiconductor material and rather large contact openings through the insulation overlying these conductive areas in order to accommodate mask alignment tolerances. This results in low density devices requiring a relatively large chip area.
With the rapid increase in the number of MOSFET elements in large-scale integrated circuit devices, efforts have been made to reduce not only the size of each element but also the size of the required contacts.
One method of increasing the density of semiconductor devices and reducing the problem of mask alignment is to form "self aligned" contact openings utilizing oversized contact masks. In general, self-aligned contacts are formed by utilizing an oversized contact mask, thus eliminating the difficulties of mask alignment. The contact is formed within the contact opening of the contact mask such that the contact is completely contained within the region to be contacted, thus eliminating short circuits to adjacent areas. In other words, the contact is self aligned because even though the oversized contact mask may expose regions surrounding the region to be contacted, the contact formed is completely within the region to be contacted. In the prior art, the perimeter of the contact opening is bounded on at least one side (and often three sides) by field oxide, even though the oversized contact mask exposes a portion of the field oxide adjacent to the contact. Such a device is described, for example, in U.S. Pat. No. 3,648,125 at column 9, lines 59-66, and also in U.S. Pat. No. 3,913,211 and 3,936,858. However, in such prior art devices, the self alignment feature is only available with regard to contact edges bounded by field oxide. Contact edges adjacent to gate regions or interconnects may not be formed in a self aligned fashion in accordance with these prior art methods.
A second attempt to solve part of this problem described in J. Electrochem. Soc. Solid State Science and Technology, Vol. 125, No. 3, March 1978, pp. 471-472, is to provide a gate material of polycrystalline silicon which is coated on its sides and top with a thin silicon dioxide (SiO.sub.2) layer which serves as an electrical insulation between the polycrystalline silicon gate and metallization interconnects formed above the gate regions. However, this proved to be unsatisfactory because it failed to eliminate short circuits due to breakdowns or fractures of the SiO.sub.2 layer created during subsequent processing. The use of a thin oxide layer on the top and sides of the gate electrode is also disclosed in U.S. Pat. Nos. 4,103,415 and 4,169,270.